The present invention relates to a solid-state imaging device, a driving method thereof, and an imaging apparatus using the same.
As solid-state imaging devices, there have been proposed complementary metal oxide semiconductor (CMOS) image sensors implementing a column-parallel AD conversion scheme (hereinafter called “column AD conversion scheme”) in which pixels are two-dimensionally arranged in a matrix form with one Analog-to-Digital converter (ADC) provided for each column.
Furthermore, in recent years, CMOS image sensors implementing a column AD conversion scheme suitably improved for image pickup at high-speed have been proposed. For example, Japanese Unexamined Patent Application Publication No. 2005-278135 discloses a CMOS image sensor implementing a column AD conversion scheme, which has achieved higher frame rate and high resolution without increasing its circuitry scale by using an up/down counter.
FIG. 1 shows a simple configuration example of the CMOS image sensor implementing a column AD conversion scheme, in which a pixel signal of each of the pixels arranged two-dimensionally in a matrix form are inputted to the up/down counter.
A pixel (Pixel) 1 supplies an analog pixel signal responsive to an amount of light received, to a voltage comparing unit (Comp) 3. The voltage comparing unit 3 also receives a reference signal from a digital-to-analog converter (DAC) 2 as a reference voltage supplying circuit. The reference signal has a so-called ramp (RAMP) waveform in which a level (voltage) changes with time in the form of a ramp.
The voltage comparing unit 3 outputs a difference signal obtained by comparing the pixel signal from the pixel 1 with the reference signal from the DAC 2, to an up/down counter (CNT) 4. For example, if the reference signal is larger than the pixel signal, a Hi (High) difference signal is supplied to the up/down counter 4, whereas if the reference signal is smaller than the pixel signal, a Lo (Low) difference signal is supplied to the up/down counter 4.
During a Pre-Charge Phase (P-phase) ADC enable period, the up/down counter (CNT) 4 down-counts only a period in which the Hi difference signal is supplied. During a Data Phase (D-phase) ADC enable period, the up-down counter 4 up-counts only a period in which the Hi difference signal is supplied. The P-phase ADC enable period is a period for measuring a reset component ΔV which is a fluctuation component of the pixel 1, whereas the D-phase ADC enable period is a period for measuring (signal component Vsig+reset component ΔV). By combining a count during the P-phase ADC enable period and a count during the D-phase ADC enable period, only the signal component Vsig is obtained from (signal component Vsig+reset component ΔV)−(reset component ΔV). This is how CDS processing is achieved.
FIG. 2 is a schematic diagram showing a detailed configuration of the voltage comparing unit 3.
The voltage comparing unit 3 includes an analog circuit 11 and a logic circuit (digital circuit) 12.
In the analog circuit 11, the pixel signal from the pixel 1 is inputted to a comparator 23 via a capacitive element 21, and the reference signal from the DAC 2 is inputted to the comparator 23 via a capacitive element 22. The comparator 23 outputs the difference signal between the pixel signal and the reference signal, and an inverter 24 inverts and amplifies the difference signal, and outputs the resultant signal to the logic circuit 12.
In the logic circuit 12, the difference signal from the inverter 24 of the analog circuit 11 is inverted and amplified by an inverter 25, and the resultant signal is outputted to the up/down counter 4. The inverter 25 can be constructed by combining, e.g., a PMOS transistor and an NMOS transistor.
In the voltage comparing unit 3 constructed above, a preprocessing for generating the difference signal is performed to cancel an input offset between the pixel signal and the reference signal. The preprocessing is a processing for bringing two input nodes of the comparator 23 into conduction. This processing is called “autozero (AZ) processing”.
Referring to FIGS. 3A and 3B, signals within the voltage comparing unit 3 during the CDS processing and the AZ processing which is a pre-processing thereof will be described. FIG. 3A is a schematic diagram showing a configuration of the voltage comparing unit 3, and FIG. 3B is a waveform diagram showing the circuit operation of a pixel.
During an AZ processing period, an AZ control signal becomes active (High), thereby making the potentials of the pixel signal and the reference signal inputted to the comparator 23 equal to cancel the input offset therebetween. It is noted in FIG. 3B that the vertical axis is common to the pixel signal and the reference signal and that the pixel signal overlaps with the reference signal having the same potential during periods indicated by a dotted line in which the pixel signal is not shown.
In the up/down counter 4 of the subsequent stage, down-counting is performed during a period in which the reference signal is larger than the pixel signal, of the P-phase ADC enable period defined by a P-phase ADC enable pulse (not shown), and up-counting is performed during a period in which the reference signal is larger than the pixel signal, of the D-phase ADC enable period defined by a D-phase ADC enable pulse (not shown).